The present invention relates generally to the field of integrated circuits, and more particularly to a system and method of generating timing signals in interleaved and/or double-sample circuits to eliminate timing skew or timing mismatch errors associated therewith.
Analog to digital converters (ADCs) are important analog circuit devices which take an analog input signal and generate one or more digital signals which are representative of the analog input. ADCs are used in many applications such as communications applications in which the components receive a voice input (an analog input) and transform the voice data into a digital format for subsequent processing.
In many telecommunication applications, high-speed, high-resolution ADCs are needed. High resolutions of 14 bits or greater have been achieved using over-sampling sigma-delta converters and pipelined converters, but the signal bandwidth is typically limited to a few megahertz (MHz). By using time-interleaved ADCs, high sampling rates can be achieved. Note that in prior art FIG. 1, a traditional non-interleaved ADC system 10 is illustrated. In the ADC system 10, an analog input signal 12 is sampled by the ADC at a sampling frequency fS to provide a digital type output 14. Note, however, that the ADC system 10 is limited by how fast the circuitry therein can operate. Therefore the sampling frequency fS is limited, thereby limiting the conversion rate thereof.
Turning now to prior art FIG. 2, the conversion rate of an ADC system 20 is increased substantially by a time-interleaving technique, wherein several ADCs, 22, 24 and 26 operate in parallel using different clock phases 27, 28 and 29, respectively. This time-interleaving technique enables a higher conversion speed since each of the individual ADCs 22, 24 and 26 need only operate at a sampling rate fS/N, wherein N is an integer representing the number of parallel-operating ADCs. Each of the digital outputs 30 from the ADCs 22, 24 and 26 are then brought together to form a digital output 32 via a multiplexer 34, as illustrated. Thus the system 20 provides a total sampling frequency of fS, while each of the individual ADCs need only operate at fS/N. Thus the total sampling frequency fS may be increased.
The performance of the time-interleaved converter system 20 of prior art FIG. 2 is limited by the accuracy of each channel ADC 22, 24 and 26; however, there are additional errors that may arise in the sampled output 32 which are caused by mismatch between the channels. The three chief types of mismatch associated with time-interleaved converters are offset mismatch, gain mismatch and timing mismatch (which is often referred to as phase skew error). The offset and gain mismatch errors are relatively easy to resolve, for example, via calibration in either the analog or digital domain. Phase skew errors, however, are not easily calibrated, since dynamic input signals are required to measure the delay skews. Furthermore, even a small phase skew of as little as 25 ps may limit the input frequency of a 10-bit converter to less than 10 MHz.
Due to the difficulties in calibrating delay skews, a passive sampling technique has been employed in conventional circuits. For example, as illustrated in FIG. 3, an ADC system 40 employs passive sampling circuits such as sample and hold circuits 42, 44 and 46 in series with each of the sub-ADCs 22, 24 and 26, respectively. Each of the sample and hold circuits 42, 44 and 46 are operable to sample the analog input 12 based on their unique clock phase (xcfx861, xcfx862, . . . xcfx86N). Although the solution 40 of prior art FIG. 3 does reduce phase skew error, such phase skew error or timing mismatch is not fully eliminated; instead such error still exists when the N different clock phases themselves are generated to drive the sample and hold circuits 42, 44 and 46. Even small differences in delay between the various clock phases may generate substantial distortion at high signal frequencies.
The sample and hold circuits 42, 44 and 46 discussed above in conjunction with the exemplary system of prior art FIG. 2 are single sample type circuits, in which a single sample of the analog input is taken for each clock cycle of its respective sampling clock (e.g., xcfx861 for circuit 42). In order to further improve the sampling speed of sample and hold circuits, a double-sampling type sample and hold circuit has been developed, as illustrated in prior art FIG. 4 and designated at reference numeral 50. The circuit 50 uses both the rising edge and falling edge of a sampling clock (and thus generally opposite or complimentary phases xcfx861 and xcfx862) to efficiently utilize an op-amp 52 associated therewith. For example, when xcfx861 xcfx861 is high, the analog input 12 is sampled on C1, while C2 is holding a previous sample via a feedback connection of the op-amp 52. Similarly, when xcfx862 goes high and xcfx861 goes low, the input 12 is sampled on C2 while the sample previously associated with C1 is held via the op-amp feedback configuration.
Note, however, that two additional signals xcfx861P and xcfx862P drive respective switches 54 that selectively couple the second terminal of the capacitors C1 and C2, respectively, to circuit ground. These signals are pre-phase signals and initiate the sample instant when their signals go low, such that the respective capacitor is decoupled from ground. Shortly thereafter, the corresponding switch 56 connected to the input 12 is turned off, and the respective switches 58 and 60 are turned on, thus connecting the respective sampling capacitor into the feedback loop. This technique is referred to as bottom plate sampling and aids in avoiding signal dependent errors which may otherwise occur if the sample had been taken by first closing the switches 56 between the capacitors C1 and C2 and the input 12.
As can be seen from the above, the double-sampled circuit 50 has two parallel signal paths and timing mismatch therebetween may introduce some errors at the output. For example, timing skew in the clock signals for the parallel channels leads to non-uniform sampling. Such timing skew may result from unmatched propagation delays from a clock generator circuit to the switches or may originate within the clock generator itself. One exemplary prior art clock signal generator is illustrated in prior art FIGS. 5 and 6, and is designated at reference numeral 70. As illustrated in FIG. 5, the clock generator circuit 70 is operable to take a single input clock signal CLK and generate four phase signals xcfx861, xcfx861P, xcfx862 and xcfx862P associated therewith.
As illustrated in prior art FIG. 6, an input clock signal xcfx86 72 and its compliment xcfx86Z 74 each drive parallel signal paths which employ a cross-coupled feedback feature via signals 75 and 76, as illustrated. In the clock generator circuit 70 of prior art FIG. 6, the pre-phase signals xcfx861P and xcfx862P are a function of the cross-coupled feedback loops and have differing pulse widths, as illustrated in the timing diagram of FIG. 7. Therefore the falling edge 78 of xcfx861P and the falling edge 79 of xcfx862pare skewed with respect to an ideal sampling clock, running at twice their frequency, and defining the sampling times for the input signal 12 of FIG. 3. This difference causes a systematic periodic sampling pattern, which results in a phase modulation of the input samples and thus leads to harmonic distortion on the output of the double-sample circuit 50 of prior art FIG. 4.
One conventional solution to the above problem is illustrated in prior art FIG. 8, wherein a double-sampled sample and hold circuit 80 is provided. The circuit 80 is similar to the circuit 50 of prior art FIG. 4, except that the switches 54 are no longer driven by pre-phase signals xcfx861P and xcfx862P, but instead are driven by standard signals xcfx861 and xcfx862. The timing instant of each sample in circuit 80, however, is not dictated by xcfx861 and xcfx862, but instead is dictated by a global sampling clock signal xcfx86g which drives a switch 82 that is in series with each of the switches 54. Therefore, the sampling instant for both C1 and C2 is dictated by the falling edge of xcfx86g, the same clock signal, and therefore the phase modulation of the input samples and the output harmonic distortion associated therewith is eliminated.
The circuit 80 of prior art FIG. 8 overcomes some problems, however, the solution also creates new performance difficulties. In circuit 80, two switches (switch 54 and switch 82) are connected in series from a capacitor terminal to circuit ground. The additional switch 82 introduces additional parasitic capacitance which causes distortion on the output which can not be removed. Therefore the circuit solution 80 of prior art FIG. 8 is unsatisfactory.
There is a need in the art for a method of providing high speed sampling without harmonic distortion on the output of sampling circuits.
The present invention relates generally to a high speed sample and hold system which reduces substantially or eliminates completely harmonic distortion due to timing mismatch or skew associated therewith.
According to one aspect of the present invention, a clock generator circuit is disclosed which provides clock signals which may be employed in double-sampled sample and hold circuits to control a switching network for sampling an analog signal on two generally parallel sampling circuits in an alternating fashion. The clock generator circuit also generates pre-phase signals which dictate a sampling instant associated with the respective sampling circuits. In contrast with conventional clock generation circuits, the pre-phase signals of the clock generator circuit of the present invention are not derived from within a set of cross-coupled feedback loops, but instead having a timing which is dictated by a global clock signal. Therefore the falling edges of the pre-phase signals which are used to define the sampling instants are both dictated by the global sampling clock and thus timing mismatch and any phase modulation associated therewith is reduced or eliminated altogether.
According to another aspect of the present invention, a clock generator circuit comprises a clock generator subcircuit which is operable to generate two phase clock signals which may be used to control a sampling of an analog signal and a hold of such sample among two generally parallel sampling circuits which interface with an operational amplifier via a switching network. In the above manner, the two phase clock signals are operable to sample the analog signal on a capacitor associated with one of the sampling circuits while a previous sample is held by the other sampling circuit in a feedback configuration with the operational amplifier. Further, the two phase clock signals are operable to switch such functionality between the generally parallel sampling circuits in an alternating fashion to thereby make efficient use of the operational amplifier.
The clock generator circuit further comprises a pre-phase clock generator subcircuit which is operably associated with the clock generator subcircuit. The pre-phase clock generator subcircuit is operable to generate two pre-phase clock signals, wherein each of the pre-phase signals is associated with a respective one of the generally parallel sampling circuits and are operable to define a sampling instant by controlling a switch in the respective sampling circuit which decouples a sampling capacitor from a predetermined potential such as circuit ground. The pre-phase clock generator subcircuit is operable to generate the pre-phase signals such that a determinative signal transition thereof occurs before a signal transition of each respective phase clock signal generated by the clock generator subcircuit, and such pre-phase signals have a falling edge timing that is dictated by a global sampling clock, thereby advantageously reducing or eliminating timing mismatch between the generally parallel sampling circuits.
In accordance with yet another aspect of the present invention, the pre-phase clock generator subcircuit further comprises a pulse generator circuit coupled to the global sampling clock and operable to generate a pulse having a timing associated therewith. The pre-phase clock generator subcircuit further comprises a pull down circuit operably coupled to the pulse generator circuit which is operable to pull nodes associated with the clock generator subcircuit down to low logic states, and from which logic states the respective pre-phase signals are generated.
Thus the present invention avoids harmonic distortion due to timing mismatch or skew associated with conventional solutions which relied upon a global sampling switch in double-sampled sample and hold circuits to avoid sampling error (but which instead created distortion due to the additional parasitic capacitance of the added global sampling switch). The present invention instead generates pre-phase signals in the clock generator circuit with a global clock signal. Therefore a timing of the global falling edge of each pre-phase signal which defines the sampling instant is dictated by the same global clock signal, which prevents sampling error in the parallel sampling circuits and harmonic distortion associated therewith.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.